1. Field of the Invention
The present invention relates to an apparatus and method for designing a circuit comprising a clock tree synthesis (hereinafter, referred to as CTS) and in particular, to an apparatus and method for converting logical connection information of a circuit comprising a clock tree synthesis.
2. Description of the Prior Art
A prior art will be explained with reference to FIG. 7 showing a conventional circuit comprising a CTS, FIG. 8 showing a general structure of a CTS, and FIG. 9 showing a conventional circuit comprising a CTS and a PLL (Phase-Locked Loop).
In the area of designing a synchronous circuit, it is common to adopt a CTS in order to reduce clock skews which are time differences among delays from a clock signal inputted to a primary clock terminal CLK to a clock signals supplied to clock terminals C of flip-flops of sequential circuits.
Referring to FIG. 8, a CTS is composed of a plurality of buffers B which are connected in tree configuration by serial-parallel connection. A clock signal supplied to a terminal CI is outputted from terminals CO while keeping the same logical level. At the stage of designing a layout of an LSI, in order to reduce clock skews, locations of buffers B, the length of each line between buffers B, and the length of each line between each buffer B and each flip-flop of each sequential circuit are finely adjusted.
Although a CTS has an advantage that the CTS can reduce clock skews, the CTS has a disadvantage that propagation delay time thereof is long because clock signals pass through multistage buffers B.
There is a method for shortening the propagation delay times of a CTS by combining a PLL with the CTS as shown in FIG. 9. According to this method, the phase of clocks supplied to flip-flops of sequential circuits coincide with the phase of a clock CLKO presenting on an output node of clock terminal CLK by feeding back one of the clocks supplied to the flip-flops to the PLL. Thus, propagation delay time in the PLL and the CTS substantially becomes zero.
In the prior art as shown in FIG. 7, because the propagation delay times in CTS are long, a period from a time when a clock signal at clock terminal CLK changes to a time when an output signal from an output terminal for synchronization output (hereinafter, referred to as clock synchronous output terminal) changes becomes long. Therefore, it is difficult to make the period satisfy a desired standard.
The reason why the propagation delay time in a CTS is long is as explained above. That is, the reason is that a clock signal inputted to node CI passes through multistage buffers B which are in serial-parallel connection in the CTS to output from node CO as shown in FIG. 8.
In the case of combining a PLL with a CTS as shown in FIG. 9, because a propagation delay time in the PLL and the CTS is substantially zero, it is easy to make an output delay time at a clock synchronous output terminal satisfy a desired standard. However, a problem arises that the area of an LSI chip increases due to the introduction of the PLL. In addition, another problem arises that a clock which coincides in phase with a clock at terminal CLK do not present at node CO in a state of clock halt or at the beginning of operation because the PLL has a minimum operation frequency to operate normally. The latter problem renders the inner state of the LSI not ensured.
According to a standard of PCI (Personal Computer Interface) which is adopted as a standard local bus of personal computers, the maximum output delay time is strictly limited and the inner state of LSIs must be ensured in a state of clock halt and at the beginning of operation. Therefore, the method of combining a PLL with a CTS hardly meets the standard of PCI.
In order to overcome the aforementioned disadvantages, the present invention has been made and accordingly, has an object to provide an apparatus for converting logical connection information of a circuit which apparatus makes an LSI chip ensured in inner state in a state of clock halt and at the beginning of operation, not increased in area, and shortened in output delay time at clock synchronous output terminals.
According to a first aspect of the present invention, there is provided an apparatus for converting logical connection information of a circuit comprising a clock tree synthesis, the apparatus comprising: a specific sequential circuit element detector which inputs first logical connection information in which connections among logical elements are described, a logical element library in which information as to whether each logical element is a sequential circuit element or a combinational circuit, information as to whether each terminal of each logical element is an input terminal or an output terminal, and information as to whether each terminal is a clock control terminal or not are included, and an output terminal list in which specific output terminals are described, and detects sequential circuit elements by using the first logical connection information, the logical element library, and the output terminal list, each of which has a clock control terminal connected to an output node of the clock tree synthesis, and an output terminal which is, directly or via a combinational circuit, connected to one of the specific output terminals; and a clock signal replacer which replaces an output node of the clock synthesis tree which is connected to the clock control terminal of each of the detected sequential circuit elements by an input node of the clock synthesis tree, and outputs second logical connection information of the circuit which is logically equivalent to the first logical connection information of the circuit.
According to a second aspect of the present invention, there is provided an apparatus for converting logical connection information of a circuit comprising a clock tree synthesis, the apparatus comprising: a specific sequential circuit element detector which inputs first logical connection information in which connections among logical elements are described, a logical element library in which information as to whether each logical element is a sequential circuit element or a combinational circuit, information as to whether each terminal of each logical element is an input terminal or an output terminal, and information as to whether each terminal is a clock control terminal or not are included, and an output terminal list in which specific output terminals and a period for each of the specific output terminals are described, and detects sequential circuit elements by using the first logical connection information, the logical element library, and the output terminal list, each of which has a clock control terminal connected to an output node of the clock tree synthesis, and an output terminal which is, directly or via a combinational circuit, connected to one of the specific output terminals; a logic designer which designs a logical element composed of a part of logical elements in the logical element library, an output node of the logical element being logically identical with an output node of the clock tree synthesis, and a delay time of the logical element from an input node of the clock tree synthesis being shorter than the clock tree synthesis""s propagation delay time by the period of each of the specific output terminals; and a clock signal replacer which replaces an output node of the clock synthesis tree which is connected to the clock control terminal of each of the detected sequential circuit elements by the output node of the logical element designed by the logic designer, and outputs second logical connection information of the circuit which is logically equivalent to the first logical connection information of the circuit.
According to a third aspect of the present invention, there is provided an apparatus for converting logical connection information of a circuit comprising a clock tree synthesis, the apparatus comprising: a specific sequential circuit element detector which inputs first logical connection information in which connections among logical elements are described, a logical element library in which information as to whether each logical element is a sequential circuit element or a combinational circuit, information as to whether each terminal of each logical element is an input terminal or an output terminal, and information as to whether each terminal is a clock control terminal or not are included, and an output terminal list in which specific output terminals and a period for each of the specific output terminals are described, and detects sequential circuit elements by using the first logical connection information, the logical element library, and the output terminal list, each of which has a clock control terminal connected to an output node of the clock tree synthesis, and an output terminal which is, directly or via a combinational circuit, connected to one of the specific output terminals; a logic designer which designs a logical element composed of a part of logical elements in the logical element library, an output node of the logical element being logically identical with an output node of the clock tree synthesis, and a delay time of the logical element from an input node of the clock tree synthesis being the same as the period of each of the specific output terminals; and a clock signal replacer which replaces an output node of the clock synthesis tree which is connected to the clock control terminal of each of the detected sequential circuit elements by the output node of the logical element designed by the logic designer, and outputs second logical connection information of the circuit which is logically equivalent to the first logical connection information of the circuit.
These and other objects, features and advantages of the present invention will become more apparent in the light of the following detailed description of the best mode embodiments thereof, as illustrated in the accompanying drawings.